 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 450/sec precision angular rate sensor data sheet ADIS16136 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no licen se is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.3 29.4700 www.analog.com fax: 781.461.3113 ? 2011 analog devices, inc. all rights reserved. features digital gyroscope system, 450/sec measurement range in - run bias stability, 4 /hour autonomous operation and data collection no external configuration commands required start - up time: 18 0 ms; sleep mode recovery: 2. 5 ms factory calibrated sensitivity and bias calibration temperature range: ?40c to + 70 c spi - compatible serial interface wide bandwidth: 380 hz embedded temperature sensor programmable operation and control a utomatic and manual bias correction controls digital filters: bartlett fir, average/decimation internal sample rate: up t o 2048 sps digital i/o: data ready, alarm indicator, general - purpose alarms for condition monitoring sleep mode for power management enable external sample clock input: up to 2048 hz single - supply operation: 4. 75 v to 5.2 5 v 2000 g shock survivability operating temperature range: ?40c to + 8 5c applications precision instrumentation platform stabilization and control industrial vehicle n avigation downhole instrumentation robotics general description the ADIS16136 i sensor? is a high performance, digital gyro - scope sensing system that operates autonomously and requires no user configuration to produ ce accurate rate sensing data. i t provides performance advantages with its low noise density, wide bandw idth, and excellent in - run bias stability, which enabl e a pplicatio ns such as platform control, navigation, robotics, and medical instrumentation. this sensor system combines industry leading i mems? technology with signal conditioning that optimizes dynamic performance. the factory calibration characterizes the entire sen sor signal chain for sensitivity and bias over a temperature range of ?40c to + 70 c. as a result, each ADIS16136 has its own unique correction for - mulas to produce accurate measurements upon installation. fo r some systems, the factory calibration eliminates the need for system level calibration and greatly simplifies it for others. the ADIS16136 provides data at rate s of up to 2 048 sps and offers an averaging/ de cimation filter structure for optimizing noise /bandwidth trade - offs. the serial peripheral interface (spi) and user register structure provide easy access to configuration controls and calibrated sensor data for embedded processor platforms. the 36 mm 44 mm 14 mm package provides four holes for simple mechanical attachment, using m2 (or 2 - 56 standard size ) machi ne screws along with a standard 24- pin, dual r ow, 1 mm pitch connector that supports electrical attachment to a printed circuit board (pcb) or cable system. functional block dia gram figure 1. ADIS16136 calibration alarms i/o self-test user control registers spi port output data registers clock mems sensor temp sensor power management cs sclk din dout gnd vdd dio1 dio4/clkin dio2 dio3 rst controller filter 10249-001
ADIS16136 data sheet rev. a | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing specifications .................................................................. 4 ? absolute maximum ratings ....................................................... 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ............................. 6 ? typical performance characteristics ............................................. 7 ? theory of operation ........................................................................ 8 ? reading sensor data .................................................................... 8 ? output data registers .................................................................. 9 ? device configuration .................................................................. 9 ? user registers .................................................................................. 10 ? digital processing configuration ................................................. 11 ? internal sample rate .................................................................. 11 ? input clock configuration ........................................................ 11 ? digital filtering ........................................................................... 11 ? averaging/decimation filter .................................................... 12 ? calibration ....................................................................................... 13 ? automatic bias correction (autonull) .................................... 13 ? manual bias correction ............................................................ 13 ? alarms .............................................................................................. 14 ? static alarm use ......................................................................... 14 ? dynamic alarm use .................................................................. 14 ? alarm reporting ........................................................................ 14 ? system controls .............................................................................. 15 ? global commands ..................................................................... 15 ? memory management ............................................................... 15 ? general-purpose input/output................................................ 15 ? self test ........................................................................................ 16 ? power management ................................................................... 16 ? status ............................................................................................ 16 ? product identification ................................................................ 17 ? applications information .............................................................. 18 ? power supply considerations ................................................... 18 ? prototype interface board ......................................................... 18 ? installation tips .......................................................................... 19 ? packaging and ordering information ......................................... 20 ? outline dimensions ................................................................... 20 ? ordering guide .......................................................................... 20 ? revision history 11/11rev. 0 to rev. a changes to functional times parameters, table 1 ...................... 3 10/11revision 0: initial version data sheet ADIS16136 rev. a | page 3 of 20 specifications t a = 25c, v dd = 5.0 v, angular rate = 0/sec, dynamic range = 45 0/sec , 1 g , unless otherwise noted. table 1 . parameter test conditions/comments min typ max unit gyroscopes dynamic range 450 480 /sec initial sensitivity gyro_out , gyro_out2 (24 bits) 7.139x10 ?5 /sec/lsb initial sensitivity tolerance 1 % sensitivity temperature coefficient ?40c t a +70c , 1 35 ppm/c nonlinearity best fit straight line , 400/sec 0.0 5 % of fs initial bias error 1 0.15 /sec bias temperature coefficient ?40c t a +70c , 1 0.00125 /sec / c in - run bias stability 25c , smpl_prd = 0x00 0f 4 /hr angular random walk 1 , 25c 0. 1 67 /hr linear acceleration effect on bias 1 0.017 /sec/ g bias voltage sensitivity vdd = 4. 7 5 v to 5. 2 5 v , 1 0.08 /sec/v misalignment axis -to - frame (package) 1.0 degrees output noise no filtering 0.11 /sec rms rate noise density f = 25 hz, no filtering 0.00357 /sec/hz rms 3 db bandwidth 3 80 hz sensor resonant frequency 15.5 17.5 20 khz logic inputs 1 input high voltage, v ih 2.0 v input low voltage, v il 0.8 v logic 1 input current, i ih v ih = 3.3 v 0.2 1 a logic 0 input current, i il v il = 0 v all pins except rst 40 60 a rst pin 80 a input capacitance, c in 10 pf digital outputs 1 output high voltage, v oh i source = 1.6 ma 2.4 v output low voltage, v ol i sink = 1.6 ma 0.4 v flash memory endurance 2 10,000 cycles data retention 2 t j = 85c 20 years functional times 3 time until data is available power - on start - up time 245 ms reset recovery time 128 ms sleep mode recovery time 2.5 ms flash memory update 7 2 ms flash memory self test 21 ms automatic sensor sel f t est time smpl_prd 0x0000 110 ms conversion rate 680 4 2048 ksps clock accuracy smpl_prd = 0x00 0f 3 % sync input clock smpl_prd = 0x0000 680 4 2048 khz power supply operati ng voltage range, vdd 4.7 5 5.0 5.25 v power supply current smpl_prd = 0x001f 1 20 ma sleep mode 1.4 ma 1 the digital i/o signals are driven by an internal 3.3 v supply , and the inputs are 5 v tolerant. 2 jedec standard 22 , method a117 . endurance measured at ?40 c , +25 c , +85 c, and +125 c. 3 these times do not include thermal settling and internal filter response times, which may affect overall accuracy. 4 the sync input clock and internal sampling clock function below the specified minimum value, at reduced performance levels. ADIS16136 data sheet rev. a | page 4 of 20 timing specification s t a = 25c, vdd = 5 v, unless otherwise noted. table 2. normal mode parameter description min 1 typ max unit f sclk serial clock 0.01 2. 5 mhz t stall stall period between data , see figure 3 15 s t readrate read rate 25 s t cs chip select to clock edge 48.8 ns t dav dout valid after sclk edge 25 ns t dsu din setup time before sclk rising edge 24.4 ns t dhd din hold time after sclk rising edge 48.8 ns t sclkr , t sclkf sclk rise and fall times 5 12.5 ns t dr , t df dout rise and fall times 5 12.5 ns t sfs cs high after sclk edge 0 ns t 1 input sync positive pulse width 5 s t 2 input sync to data ready output 300 s t 3 input sync period 488 s t x input sync low time 100 s 1 guaranteed b y design and characterization but not tested in production . timing diagrams figure si timing and seuence figure stall time and data rate figure input clock timing diagram cs sclk dout din 1 2 3 4 5 6 15 16 r/w a5 a6 a4 a3 a2 d2 msb db14 d1 lsb db13 db12 db10 db11 db2 lsb db1 t cs t sfs t dav t dhd t dsu 10249-002 cs sclk t readrate t stall 10249-003 t 3 t x t 2 t 1 sync clock (clkin) data ready 10249-004 data sheet ADIS16136 rev. a | page 5 of 20 absolute maximum rat ings table 3. parameter rating acceleration any axis, unpowered 2000 g any axis, powered 2000 g vdd to gnd ? 0.3 v to + 6.0 v digital input voltage to gnd ?0.3 v to +5.3 v digital output voltage to gnd ?0.3 v to vdd + 0.3 v operating temperature range ?40c to + 8 5c storage temperature range ?65c to +125c 1, 2 1 extended exposure to temperatures outside the specified temperature range of ?40c to +105c can adversely affect the accuracy of the factory calibration. for best accuracy, store the device s within the specified operating range of ?40c to +105c. 2 although the device is capable of withstanding short term exposure to 150c, long - term exposure threatens internal mechanical integrity. table 4 . package characteristics package typ e ja jc device weight 24 - lead module with connector interface 15.7 1.48 25 g esd caution stress es a bo ve thos e l isted under absolute maxim um ratin gs ma y c ause permanent damage to the device. this is a stress rating only; fu nctional operation of the d ev ice at these or any other co nditio ns abo ve those indicated in the operatio na l section of th is speci fi cat ion is not implied. expo su re to absolu te ma ximum rat in g conditions fo r e xtended periods may a ff ect de vi ce reliability. ADIS16136 data sheet rev. a | page 6 of 20 pin configuration and function descripti ons figure 5. mating connector pin assignments figure 6 . axial orientation (bottom side facing up) table 5 . pin function descriptions pin no. mnemonic type 1 description 1 dio3 i/o configurable digital input/output. 2 dio4/ clkin i configurable digital input/output/ clock i nput (smpl_prd = 0x0000). 3 sclk i spi serial clock. 4 dout o spi data output. clocks output on sclk falling edge. 5 din i spi data input. clocks input on sclk rising edge. 6 cs i spi chip select. 7 dio1 i/o co nfigurable digital input/output. 8 rst i reset. 9 dio2 i/o c onfigurable digital input/output. 10, 11, 12 vdd s power supply. 13, 14, 15 gnd s power ground. 16 to 24 dnc n/a do not connect. do not connect to these pins. 1 i/o is input/output, i is input, o is output, s is supply, n/a is not applicable. 13 14 11 12 9 10 7 8 5 6 3 4 1 2 15 16 17 18 19 20 21 22 23 24 ADIS16136 top view notes 1. pins are not visible from this view. the pin assignments shown represent the mating connector assignments. 2. use samtec clm-112-02 or equivalent. 10249-005 rate axis positive rotation direction + 10249-006 data sheet ADIS16136 rev. a | page 7 of 20 typical performance characteristics figure 7. root allan variance, 5 v, 25c, 1024 sps figure 8. sensitivity error vs. temperature, ? 40 c to +75 c to ? 40 c figure 9. offset ( bias ) error vs. temperature, ? 40 c to +75 c to ? 40 c 1 10 100 0.01 0.1 1 10 100 1000 10000 root allan v ariance (/hr) t au (seconds) +1 average C1 10249-025 ?0.60 ?0.40 ?0.20 0 0.20 0.40 0.60 ?45 ?35 ?25 ?15 ?5 5 15 25 35 45 55 65 75 sensitivity error (%) tempera ture (c) initial sensitivity error = 0.35% sensitivitiy tempc = 25ppm/c 10249-026 tempera ture (c) ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 offset error (/sec) initial bias error = 0.1 bias temperature coefficient = 0.00125/sec/c 10249-027 ADIS16136 data sheet rev. a | page 8 of 20 theory of operation the ADIS16136 is an autonomous system that requires no user initialization. as soon as it has a valid power supply, it initializes and starts sampling, processing , and loading sensor data into the output register s. a fter each sample cycl e concludes, dio1 pulses high . the spi interface enables simple integration with many embedded processor platforms , as shown in figure 10 (electrical connection) and table 6 ( processor pin names and functions ). figure 10 . electrical connection diagram table 6 . generic master processor pin names and functions pin name function ss slave select irq interrupt request mosi master output, slave input miso master input, slave output sclk serial clock the ADIS16136 spi interface supports full duplex serial communication (simultaneous transmit and receive) and uses the bit sequence shown in figure 13. table 7 provides a list of the most common settings that require attention to initialize a processor serial port for the ADIS16136 spi interface. table 7 . generic master processor spi settings processor setting description master ADIS16136 operate s as a s lave sclk rate 2 mhz maximum serial clock rate spi mode 3 cpol = 1 (polarity), cpha = 1 (phase) msb first mode bit sequence 16 - bit mode shift register/data length r eading s ensor d ata a single register read requires two 16 - bit spi cycles. the first cycle requests the contents of a register using the bit assignments in figure 13 . then, the regist er contents follow on dout during the second sequence. figure 11 includes three single register reads in succession. in this example, the process starts with pin 5, din = 0x0600 , to request the contents of the gyro_out register and follows with 0x0 4 00 to request the contents of the gyro_out 2 register and with 0x0 2 00 to request the contents of the temp_out register. full duplex operation enables pro - cessors to use the same 16 - bit spi cycle to read data from dout while requesti ng the next set of data on the din pin . figure 12 provides an example of the four spi signals when reading gyro_out in a repeating pattern. figure 11 . sp i r ead e xample figure 12 . spi read example , second 16 - bit sequence figure 13 . spi communication bit sequence system processor spi master ADIS16136 sclk cs din dout sclk ss mosi miso 5v irq dio1 vdd i/o lines are compatible with 3.3v or 5v logic levels 10 6 3 5 4 7 11 12 13 14 15 10249-010 din dout 0x0600 0x0400 0x0200 gyro_out gyro_out2 temp_out 10249-0 11 dout = 1111 1001 1101 1010 = 0xf9da = ?1574 lsbs = ?29.765/sec din = 0000 0110 0000 0000 = 0x0600 cs sclk din dout 10249-012 r/w r/w a6 a5 a4 a3 a2 a1 a0 dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0 d0d1d2d3d4d5d6d7d8d9d10d11d12d13d14 d15 cs sclk din dout a6 a5 d13d14 d15 notes 1. dout bits are produced only when the previous 16-bit din sequence starts with r/w = 0. 2. when cs is high, dout is in a three-state, high-impedance mode, which allows multifunctional use of the line for other devices. 10249-013 data sheet ADIS16136 rev. a | page 9 of 20 output data register s table 8 . output data register formats register address measurement temp_out 0x02 internal temperature gyro_out 2 0x04 gyroscope , lower 16 bits gyro_out 0x06 gyroscope , upper 16 bits rotation rate (gyroscope) gyro_out is the primary register for gyroscope output data and uses 16 - bit twos complement format for its data. table 9 provides the numerical format, and table 10 provides several examples for converting digital data into /sec . table 9 . gyro_out bit descriptions bits description [15:0] gyroscope data ; t wos complemen t, 0.018275/sec pe r lsb , 0/sec = 0x0000 table 10 . gyro_out, twos complement format rotation rate decimal hex binary + 450 /sec +24,623 0x602f 0110 0000 0010 1111 +0.0365 5 /sec +2 0x0002 0000 0000 0000 0010 +0.018275 /sec +1 0x0001 0000 0000 0000 0001 0/sec 0 0x0000 0000 0000 0000 0000 ?0.018275 /sec ?1 0xffff 1111 1111 1111 1111 ?0.03655 /sec ?2 0xfffe 1111 1111 1111 1110 ? 450 /sec ?24,623 0x9fd1 1001 1111 1101 000 1 the gyro_out2 register (see table 11) captures the bit growth associated with the decimation and fir filter s that are shown in figure 18 using a msb justified format. the bit growth starts with the msb (gyro_out2[15]), is equal to the decimation rate setting in dec_rate[4:0] (see table 18 ), and grows in the lsb direction as the decimation rate increases. see figure 14 for more details. table 11. gyro_out2 bit descriptions bits description [15: 0] rotation rate data; resolution enhancement bits figure 14 . gyroscope output format, dec_rate[4:0] 0 internal temperature the temp_out register (see table 12 ) provides an internal temperature measurement that can be useful for observing relative temperature changes in the en vironment. table 13 provides several coding examples for converting the 16- bit twos complement number into units for temperature (c). table 12. temp _out bit descriptions bits description [15:0] temperature data; twos complement, 0.0 10697 c per lsb, 0c = 0x0000 table 13 . temperature, twos complement format temperature decimal hex binary +8 5c + 7946 0x1f0a 0001 1111 0000 1010 +0.0 21394 c +2 0x00 02 0000 0000 0000 0010 + 0.0 10697 c +1 0x00 0 1 0000 0000 0000 0001 0 c 0 0x000 0 0000 0000 0000 0000 ? 0.010697 c ?1 0xfff f 1111 1111 1111 1111 ?0. 021394 c ?2 0xff fe 1111 1111 1111 1110 ?40c ? 3739 0xf165 111 1 0001 01 10 01 01 d evice c onfiguration the control registers listed in table 14 provide a va riety of user configuration options. the spi provides access to these registers, one byte at a time, using the bit assignments shown in figure 13 . each register has 16 bits, wherein bits [7:0] represent the lower address and bits[15:8] represent the upper address. figure 15 provides an example of writing 0x03 to address 0x22 (dec_ rate[7:0]), using pin 5, din = 0xa203 . this example reduces the sample rate by a factor of 8 (see table 16). figure 15 . spi sequence for setting the decimate rate to 8 (din = 0xa2 03) dual memory structure writing configuration data to a control register updates its sram contents, which ar e volatile. after optimizing each relevant control register setting in a system, set glob_cmd[3] = 1 (din = 0xa808) to back up these settings in the nonvolatile flash memory. the flash back up process requires a valid power supply level f or the entire 72 ms process time. table 14 provides a user register memory map that includes a co lumn of flash backup information. a yes in this column indicates that a register has a mirror location in flash and , when backed up properly, automatically restore s itself during start up or after a reset. figure 16 pro vides a diagram of the dual memory structure that is used to manage operation and store critical user settings. figure 16 . sram and flash memory diagram gyroscope data not used d 15 0 15 0 d = dec_rate[4:0] bit weight = 0.018275 2 d lsb = gyro_out2[16-d] /sec lsb gyro_out gyro_out2 10249-014 din = 1010 0010 0000 0011 = 0xa203, writes 0x03 to address 0x22 sclk din cs 10249-015 nonvolatile flash memory (no spi access) manual flash backup start-up reset volatile sram spi access 10249-016 ADIS16136 data sheet rev. a | page 10 of 20 user registers table 14 . user register memory map name r/w flash backup address 1 default register description bit descriptions flash_cnt r yes 0x00 n/a 2 flash memory write count table 30 temp_out r no 0x02 n/a 2 output, temperature (internal) table 12 gyro_out2 r no 0x04 n/a 2 output, g yroscope , lower 16 bits table 11 gyro_out r no 0x06 n/a 2 output, gyroscope, upper 16 bits table 9 gyro_off2 r/w yes 0x08 0x0000 gyroscope bias correction, lower 16 bits table 21 gyro_off r/w yes 0x0a 0x0000 gyroscope bias correction, upper 16 bits table 20 reserved n/a 2 n/a 2 0x0c to 0x0f n/a 2 reserved alm_mag1 r/w yes 0x10 0x0000 alarm 1 trigger setting table 23 alm_mag2 r/w yes 0x12 0x0000 alarm 2 trigger setting table 24 alm_smpl1 r/w yes 0x14 0x0000 alarm 1 sample period table 25 alm_smpl2 r/w yes 0x16 0x0000 alarm 2 sample period table 25 alm_ctrl r/w yes 0x18 0x0000 alarm configuration table 26 gpio_ctrl r/w yes 0x1a 0x0000 auxilia ry digital input/output control table 32 msc_ctrl r/w yes 0x1c 0x0006 miscella neous control: data ready, self test table 31 smpl_prd r/w yes 0x1e 0x001f internal sample period (rate) control table 16 avg_cnt r/w yes 0x20 0x0000 d igital filter control table 17 dec_rate r/w yes 0x22 0x0000 decimation rate setting table 18 slp_ctrl w yes 0x24 0x0000 sleep mode control table 33 diag_stat r no 0x26 0x0000 system status table 34 glob_cmd w no 0x28 0x0000 system command table 29 reserved n/a 2 n/a 2 0x2 a to 0x31 n/a 2 reserved lot_id1 r yes 0x32 n/a 2 lot identification code 1 table 36 lot_id2 r yes 0x34 n/a 2 lot identification code 2 table 36 lot_id3 r yes 0x36 n/a 2 lot identification code 3 table 36 prod_id r yes 0x38 0x3f0 8 product id , binary number for 16 , 13 6 table 35 serial_num r yes 0x3a n/a 2 serial number table 37 1 each register contains two bytes. the address column in this table only offers the address of the lower byte. add 1 to it to calculate the address of the upper byte. 2 n/a means not applicable. data sheet ADIS16136 rev. a | page 11 of 20 d igital processing configuration figure 18 provides a block diagram for the sampling and digital filter stages inside the ADIS16136 . table 15 provides a summary of registers for sample rate and filter control. table 15. digital p rocessing r egisters register name address description smpl_prd 0x1e sample rate control avg_cnt 0x20 digital filtering and range control dec_rate 0x22 decimation rate setting internal sample r ate the smpl_prd register in table 16 provides a programmable control for the internal sample rate. use the following formula to calculate the decimal number for the code to write into this register: ( ) ;1 768,32 _ ?= s f prd smpl f s 2048 sps the factory default setting for smpl_prd sets the internal sample rate to a rate of 1024 sps; the minimum setting for the smpl_prd register is 0x000f, which results in an internal sample rate of 2048 sps. table 16 . smpl_prd bit descriptions bits description (default = 0x00 1f ) [ 15: 0] clock setting bits; sets f s in figure 18 input clock configur ation set smpl_prd = 0x0000 (din = 0x9f00, then din = 0x9e00) to disable the internal clock and enable dio4/ clkin as a clock input pin. digital filtering the avg_cnt register (see table 17 ) provides user controls for the low - pass filter. this filter contains two cascaded averaging filters that provide a bartlett window fir fil ter response (see figure 18 ). for example, set avg_cnt[7:0] = 0x04 (din = 0xa004) to set each stage to 16 taps. when used with the default sample rate of 1024 sps, this establishes a ?3 db bandwidth of approximately 24 hz for this filter. figure 17 . bartlett window fir filter frequency response table 17 . avg_cnt bit descriptions bits description (default = 0x0000) [15:3] dont care [2:0] binary; b variable in figure 18 ; maximum = 110 (6) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0.001 0.01 0.1 1 magnitude (db) frequency ( f / f s ) n = 2 n = 4 n = 16 n = 64 10249-017 ADIS16136 data sheet rev. a | page 12 of 20 averaging/decimation filter the dec_rate register (see table 18 ) provides user control for the final filter stage (see figure 18 ), which averages and decimates the output data. for systems that value lower sample rates, this filter stage provides an opportunity to lower the sample rate while maintaining optimal bias stability performance. the ?3 db bandw idth of this filter stage is approximately one half the output data rate. for example, set dec_rate[7:0] = 0x04 (din = 0xa204) to reduce the sample rate by a factor of 16. when the factory default 1024 sps sample rate is used, this decimation setting reduces the output data rate to 64 sps and the sensor bandwidth to approximately 32 hz. table 18 . dec_rate bit descriptions bits description (default = 0x0 000 ) [15: 5] dont care [4 :0] binary; d variable in figure 18 ; maximum = 100 0 0 (16) figure 18 . sampling and frequency response block diagram mems gyro 410hz 1595hz clock f s clkin n d ?3db bandwidth = 380hz b = avg_cnt[2:0] n b = 2 b n t = 2n b ? 1 nt = total number of taps sp 15 sp = smpl_prd d = dec_rate[4:0] n d = 2 d n d = number of taps n d = data rate divisor f s = 32,768 sp + 1 10249-018 data sheet ADIS16136 rev. a | page 13 of 20 calibration the ADIS16136 factory calibration produces correction formulas for the gyroscope and programs them into the flash memory. table 19 contain s a list of user control registers that provide an opportunity for user optimization after installation. figure 19 illustrates the summing function of the sensors offset correction register. table 19. registers for u ser c alibration register address description gyro_off2 0x08 gyroscope bias gyro_off 0x0a gyroscope bias glob_cmd 0x28 bias correction command figure 19 . gyroscope bias cali bration user controls the factory calibration addresses initial and temperature dependent bias errors in the gyroscopes, but some environ - mental conditions, such as temperature cycling and mechanical stress on the package, can cause bias shifts in mems gyroscope structures. for systems that value absolute bias accuracy, there are two options for optimizing absolute bias accuracy: autonull an d manual correction. automatic bias corre ction ( autonull ) set glob_cmd[0] = 1 (din = 0xa801) to start the automatic bias correction (abc) function, which uses the following internal sequence to calibrate each gyroscope for bias error: 1. wait for a complete output data cycle to complete, which includes the entire average and decimation time in dec_rate. 2. read the output registers of the gyroscope. 3. multipl y the measurement by ?1 to change its polarity. 4. write the final value into the offset registers. 5. update the flash memory. the allan variance curve shown in figure 7 provides a trade - off between bias accuracy and averaging time. the dec_rate register provides a user contro l for averaging time when using the abc function. set dec_rate[7:0] = 0x10 (din = 0xa210) , which sets the decimation rate to 65,536 (2 16 ) and provides an averaging time of 64 seconds (65,536 1024 sps) for this function . next, set glob_cmd[0] = 1 (din = 0 xa801), and keep the platform stable for at least 65 seconds while the gyroscope bias data accumulates. after this completes, the ADIS16136 automatic ally updates the flash memory. when the abc function starts, the spi is not active . the only way to interrupt the abc function is to remove power or initiate a hardware reset using the rst pin. when using dec_rate = 0x0010, the 1 accuracy for this correction is approxima tely 0.00 1/sec for the gyroscope correction factor . see table 29 for more information on glob_cmd. manual bias correcti on the gyro_off and gyro_off2 registers (see table 20 and table 21 ) provide a bias adjustment function for the outpu t of each sensor. gyro_off has the same format as gyro_out, and gyro_off2 has the same format as gyro_out2. table 20 . gyro_off bit descriptions bits description (default = 0x0000) [15:0] gyroscope offset correction; t wos complement, 0.018275 /sec per lsb table 21 . gyro_off2 bit descriptions bits description (default = 0x0000) [15: 0] gyroscope offset correction, finer resolution; uses same format as gyro_out2 (see table 11 ) restoring factory calibration set glob_cmd[1] = 1 (din = 0x a8 02) to execute the factory calibration restore function. this function resets each user calibration register to 0x0000, resets all sensor data to 0, and automatically updates the flash memory within 72 ms. see table 29 for more information on glob_cmd. mems gyro factory calibration and filtering adc gyro_out gyro_out2 gyro_off gyro_off2 10249-019 ADIS16136 data sheet rev. a | page 14 of 20 alarms the alarm function provides monitoring for two independent conditions. table 22 contains a list of registers that provide configuration and control inputs for the alarm function. table 22 . registers for alarm c onfigura t ion register address description alm_mag1 0x10 alarm 1, trigger setting alm_mag2 0 x12 alarm 2, trigger setting alm_smpl1 0x14 alarm 1, sample period alm_smpl2 0x16 alarm 2, sample period alm_ctrl 0x18 alarm configuration the alm_ctrl register (see table 26 ) provides data source selection (bits[15:8]), sta tic/dynamic setting for each alarm (bits[7:6]), trigger polarity (bits[ 5:4 ]), data source filtering (bit 3 ), and an alarm indicator signal (bits[2:0]). static alarm use the static alarms setting compares the data source selection (alm_ctrl[ 15:8]) with the values in the alm_magx registers in table 23 and table 24 . the data format in these registers matches the format of the data selection in alm_ctrl[15:8] . alm_ctrl[5 :4] provide polarity settings. see table 27 for a static alarm configuration example. table 23 . alm_mag1 bit descriptions bits description (default = 0x0000) [15:0] threshold setting ; matches format of the alm _ctrl[11:8] selection table 24 . alm_mag2 bit descriptions bits description (default = 0x0000) [15:0] threshold setting ; m atches for format of the alm_ctrl[15:12] selection dynamic alarm use the dynamic alarm setting monitors the data selection for a rate - of - change compariso n. the rate of change is represented by the magnitude in the alm_magx registers over the time represented by the number of samples in the alm_smplx register (see table 25 ). see table 27 for a dynamic alarm configuration example. table 25 . alm_smpl1, alm_smpl2 bit descriptions bits description (default = 0x0000) [15:8] not used [7:0] binary, number of samples (both 0x00 and 0x01 = 1) alarm r eporting diag_stat[9:8] provide error flags that indicate an alarm condition. alm_ctrl[2:0] provide controls for a hardware indicator using dio1 or dio2. table 26 . alm_ctrl bit descriptions bits description (default = 0x0000) [15:12] alarm 2 source selection 0000 = disable 0001 = gyro_out (does not include gyro_out2) 0010 = temp_out 0011 = diag_stat [11:8] alarm 1 source selection (same as alarm 2) 7 rate - of - change enable for alarm 2 (1 = rate of change, 0 = static level) 6 rate -of - change enable for alarm 1 (1 = rate of change, 0 = static level) 5 comparison polarity for alarm 2 (1 specifies >alm_mag2, 0 specifies data sheet ADIS16136 rev. a | page 15 of 20 system controls the ADIS16136 provides a number of system level controls for managing its operation using the registers listed in table 28. table 28 . system tool registers register name address description gpio_ctrl 0x1a general - purpose i/o control msc_ctrl 0x1c self test, calibration, data ready slp_ctrl 0x24 sleep mode control diag_stat 0x26 error flags glob_cmd 0x28 single command functions lot_id1 0x32 lot identification code 1 lot_id2 0x34 lot identification code 2 lot_id3 0x36 lot identification code 3 prod_id 0x38 product identification serial_num 0x3a serial number global commands the glob_cmd register (see table 29 ) provides trigger bits for several operations. write 1 to the a ppropriate bit in glob_cmd to start a function. after the function completes, the bit restores to 0. software reset set glob_cmd [7] = 1 (din = 0xa880) to reset the operation, which removes all data, initializes all registers from their flash settings, and starts data collection. this function provides a firmware alternative to the rst line (see table 5 , pin 8). table 29 . glob_cmd bit descriptions bits description (default = 0x0000) execution time 1 [15:8] not used n/a 7 software reset 70 ms [6:4] not used n/a 3 flash update 70 ms 2 not used n/a 1 factory calibration restore 71 ms 0 automatic bias correction n/a 2 1 n/a in this column means not applicable. 2 execution time is based on smpl_prd and dec_rate settings. this starts at the next data ready pulse, restarts the decimation cycle, and then writes to the flash (7 0 ms) after completing a decimation cycle. with respect to figure 18 , the decimation cycle time = n d f s . memory m anagement the data retention of the flash memory depends on the temper - ature, as shown in figure 20. the flash_cnt regist er (see table 30 ) provides a 16 - bit counter that helps track the number of write cycles to the nonvolatile flash memory, which helps the user manage against the e ndurance rating. the flash updates every time any of the following bits are set to 1: glob_cmd[3] , glob_cmd [1] , and glob_ cmd[0] . table 30 . flash_cnt bit descriptions bits description) [15:0] binary counter ; number of flash updates figure 20 . flash memory retention checksum test set msc_ctrl[11] = 1 (din = 0x9d08) to perform a check sum verification of the internal program memory. this takes a summa - tion of the internal program memory and compares it with the original summation value for the same locations (from factory configuration). c heck the results in the diag_stat register (see table 34 ). diag_stat[6] = 0 if the sum matches the correct value and 1 if it does not. make sure that the power supply is within specification for the entire 2 1 ms that this function takes to complete. general - purpose i nput /o utput the re are four general - purpose i/o lines, dio1, dio2, dio3, and dio4/clkin that provide a number of useful functions. the msc_ctrl[2:0] bits (see table 31 ) control the data ready configu - ration and have the highest priority for setting either dio1 or dio2 (but not both). the alm_ctrl[2:0] control bits (see table 26) provide the alarm indicator configuration control and have the second highest priority for dio1 or dio2. when dio1 and dio2 are not in use as either data ready or alarm indicator signals, the gpio_ctrl register (see table 32 ) provides the control and data bits for them, together with the dio3 and dio4 lines . data ready input/output indicator the factory default setting for msc_ctrl[2:0] is 110, which configures dio1 as a positive data ready indicator signal. a common option for this function is msc_ctrl[2:0] = 100 (din = 0x9c04), which changes data ready to a negative polarity for processors that provide only negative triggered interrupt pins. the pulse width is between 100 s and 200 s over all conditions. example i nput /o utput configuration for example, set gpio_ctrl[ 7:0 ] = 0x02 (din = 0x9a02) to set dio 1 as an input and dio2 as an output. then, set gpio_ctrl[ 15:8 ] = 0x02 (din = 0x9b02) to set dio2 in a high output state. monitor dio1 by reading gpio_ctrl[8] (din = 0x1b00). 600 450 300 150 0 30 40 retention (years) junction temperature (c) 55 70 85 100 125 135 150 10249- 1 13 ADIS16136 data sheet rev. a | page 16 of 20 table 31 . msc_ctrl bit descriptions bits description (default = 0x0006) [15:12] not used 11 memory test (cleared upon completion) (1 = enabled, 0 = disabled) 10 automatic self test (cleared upon completion) (1 = enabled, 0 = disabled) 9 manual self test (1 = enabled, 0 = disabled) 8 not used 7 disable sensor compensation (1 = disable compensation, 0 = enable compensation ) [6 :3] not used 2 data ready enable (1 = enabled, 0 = disabled) 1 data ready polarity (1 = active high, 0 = active low) 0 data ready line select (1 = dio2, 0 = dio1) table 32 . gpio_ctrl bit descriptions bits description (default = 0x0000) [15: 12 ] dont care 11 general - purpose i/o line 4 (dio 4 ) data level 10 general - purpose i/o line 3 (dio 3 ) data level 9 general - purpose i/o line 2 (dio2) data level 8 general - purpose i/o line 1 (dio1) data level [7: 4] dont care 3 general - purpose i/o line 2 (dio2) direction control (1 = output, 0 = input) 2 general - purpose i/o line 1 (dio1) direction control (1 = output, 0 = input) 1 general - purpose i/o line 2 (dio2) direction control (1 = output, 0 = input) 0 general - purpose i/o line 1 (dio1) direction control (1 = output, 0 = input) self test the msc_ctrl bits (see table 31 ) provide a self test function that helps verify the mechanical integrity of the mems and signal processing circuit. when enabled, the self test applies an electrostatic force to the internal sensor element, which causes it to move in a manner that simulates its response to actual rotation. there are two self test options in the msc_ctrl register: auto - matic and manual. set msc_ctrl[10] = 1 (din = 0x9d04) to run the automatic self test routine, which reports a pass/fail result in diag_stat[5]. msc_ctrl[10] resets itself to 0 after com - pleting this routine. this process takes approximately 45 ms. set msc_ctrl[9] = 1 (din = 9d0 2 ) to manually activate the self test function, and set msc_ctrl[9] = 0 (din = 9d00) to manually deactivate the self test function. measure the output bias for each condition, calculate the difference between them, and compare it to the expected self test response shown in table 1 . power management the slp_ctrl register (see table 33 ) provides two different s leep modes for system level management: normal and timed. set slp_ctrl[ 7:0 ] = 0xff (din = 0xa4ff ) to start normal sleep mode . to awaken the device from sleep mode, use one of the following options to restore normal operation: assert cs fr om high to low, pulse rst low, then high again, or cycle the power. use slp_ctrl[7:0] to put the device into sleep mode for a specified perio d. for example, slp_ctrl[7:0] = 0x64 (din = 0xa464) puts the ADIS16136 to sleep for 50 sec. table 33 . slp_ctrl bit descriptions bits description [15: 8] not used [7:0] 0xff: normal sleep mode 0x00 to 0xfe: programmable sleep time bits; 0.5 sec/lsb status the diag_stat register (see table 34 ) provides error flags for a number of functions. each flag uses a 1 to indicate an error condition and a 0 t o indicate a norm al condition. reading this register provides access to the status of each flag and resets all of the bits to 0 fo r monitoring future operation. if the error conditi on remains, the error flag return s to 1 at the conclu sion of the next sample cycle. the spi communication error flag in diag_stat[3] indicates that the number of sclks i n a spi sequence did not equal a multiple of 16 sclks. table 34 . diag_stat bit descriptions bits description (default = 0x0000) [15:1 0] not used 9 alarm 2 status (1 = active, 0 = inactive) 8 alarm 1 status (1 = active, 0 = inactive) 7 not used 6 flash test, checksum flag (1 = fail, 0 = pass) 5 self test diagnostic error flag (1 = fail, 0 = pass) 4 sensor over range (1 = over range, 0 = normal) 3 spi communication failure (1 = fail, 0 = pass) 2 flash update failure (1 = fail, 0 = pass) [1 :0 ] not used data sheet ADIS16136 rev. a | page 17 of 20 product identification the prod_id register (see table 35 ) contains 0x3f08, which is the hexadecimal equivalent of 16,136. the lot_id1, lot_id2, and lot_id3 registers (see table 36 ) provide manufacturing lot information. the serial_num register (see table 37) con - tains a binary n umber t h at represents the seri al number on the device label and is l ot specific. table 35 . prod_id bit descriptions bits description [15:0] product identification = 0x 3f08 (16,136) table 36 . lot_id1, lot_id2 , lot_id3 bit descriptions bits description [15:0] lot identification, binary code table 37 . serial_num bit descriptions bits description [15:14] not used [13:0] serial number, 1 to 9999 (0x270f) ADIS16136 data sheet rev. a | page 18 of 20 applications informa tion power supply conside rations the ADIS16136 includes 12 f of capacitanc e across the vdd and gnd pins. th is capacit ance present s low input impedance for power suppl ies that have fast rise times. the internal power regulator waits for a valid input supply voltage, and then go es through a start - up process that draws an elevated current (~400 ma) for approximately 1.5 ms. this transient current occurs approximately 125 ms after vdd reach es a valid level. this regulation circuit also provides a constant power load, which results in a load that has a negative dynamic resistance. figure 21 provides a gr aphical relationship between the supply current and voltage for systems that need to account for this type of load when designing supply feedback loops. figure 21 . supply current vs supply voltage prototype interface board the ADIS16136 /pcbz includes one ADIS16136 amlz, one interface pcb, and four m2 18 machine screws . the interface pcb provides larger connectors than the ADIS16136 amlz for simpler prototyping, four tapped m2 holes for attachment of the ADIS16136 amlz, and four holes (machine screw size m2.5 or no. 4) for mounting the ADIS16136 amlz to a so lid structure. j1 and j2 are dual row, 2 mm (pitch) connectors that work with a number of ribbon cable systems, including 3m part number 152212 - 0100 - gb (ribbon crimp connector) and 3m part number 3625/12 (ribbon cable). figure 22 provides the top level view of the interface board. install th e ADIS16136 am lz onto this board using the silk pattern as an orientation guide. figure 23 provides the pin assignments for j1 and j2 . the pin descriptions match those listed in table 5 . the ADIS16136 does not require external capacitors for normal operation; therefore, the interface printed circui t board (pcb) does not use the c1 and c2 pads . figure 22 . physical diagram for the ADIS16136 /pc bz figure 23 . j1 pin assignments 105 1 10 1 15 120 125 4.75 4.80 4. 85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 current (ma) supply vo lt age (v) C40?c +25?c +85?c 10249- 1 19 10249-020 i sensor ADIS16136 mounting holes rst sclk dout din gnd vdd dio2 dio4 vdd cs1 cs2 gnd gnd vdd dio1 dio3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 10249-021 data sheet ADIS16136 rev. a | page 19 of 20 installation tips figure 24 and figure 25 provide the mechanical design infor - mation used for the ADIS16136 /pcbz. use these figures when implementing a connector - down approach, where the mating connector and the ADIS16136 am lz are on the same surface. when designing a connector - up system, use the mounting holes shown in figure 24 as a guide in designi ng the bulkhead mounting system, and use figure 25 as a guide in developing the mating connector interface on a flexible circuit or other connector sy stem. the mating connector pattern in figure 25 assumes the use of the samtec clm - 112- 02 series of connectors. figure 24 . suggested mounting hole locations , connector down figure 25 . suggested layout and mechanical design for the mating connector 2x 0.560 bsc alignment holes for m a ting socket 5.00 bsc 39.60 bsc 19.800 bsc 31.200 bsc 15.600 bsc 5.00 bsc 4x 2.500 bsc 2.280 17.520 10249-022 0.4334 [11.0] 0.0240 [0.610] 0.019685 [0.5000] (typ) 0.054 [1.37] 0.0394 [1.00] 0.0394 [1.00] 0.1800 [4.57] nonplated thru hole 2 0.022 dia (typ) 0.022 dia thru hole (typ) nonplated thru hole 10249-023 ADIS16136 data sheet rev. a | page 20 of 20 packaging and ordering information outline dimensions figure 26 . 24 - lead module with connector interface (ml - 24 -3) dimensions shown in millimeters ordering guide model 1, 2 tem perature range package description package option ADIS16136a mlz ?40c to + 85c 24 - lead module with connector interface ml -24 -3 ADIS16136/pcbz interface pcb 1 z = rohs compliant part. 2 ADIS16136/pcbz includes one ADIS16136amlz and one interface pcb. for more information about the interface pcb, see figure 22 . 010908-a top view end view 35.854 35.600 35.346 31.350 31.200 31.050 15.700 15.600 15.500 44.254 44.000 43.746 39.750 39.600 39.450 1.00 bsc (lead pitch) 0.30 bsc sq (pin size) 2.200 typ 2.200 typ 2.400 thru hole (4 places) 5.50 bsc 3.27 3.07 2.87 14.054 13.800 13.546 19.900 19.800 19.700 17.670 17.520 17.370 ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10249 -0- 11/11(a) www.analog.com/ ADIS16136 |
Price & Availability of ADIS16136
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |